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the information in this document is subject to change without notice. mos integrated circuit p p p p PD29F008L 8 m-bit cmos 3.0 v-only flash memory 1 m-word by 8-bit (byte mode) preliminary data sheet document no. m12309ej2v0ds00 (2nd edition) date published september 1997 n printed in japan ? 1997 the mark shows major revised points. description the p PD29F008L is an electrically programmable/erasable high-speed 3.0 v-only flash memory with a 8,388,608- bit configuration. it possesses an automatic single byte program function and an automatic block erase function that are effected by command register input. this memory consists of 19 blocks: one protection block (16 k byte), two condition blocks (8 k byte by 2 blocks), and sixteen main blocks (32 k byte by 1 block, 64 k byte by 15 blocks). the p PD29F008L comes in two types: the type t with the protection block located at the top address and the type b with the protection block located at the bottom address. the p PD29F008L is packed in 40-pin tsop (i) (10 u 20 mm). features ? 1,048,576 words by 8 bit ? hardware reset ? two types of protection block locations ? ready (/busy) output (ry (/by)) type t : protection block at the top address ? data polling and toggle bit type b : protection block at the bottom address ? automatic erase function ? fast access time : 120, 150 ns (max.) ? functions for automatic erasure: ? fast program/erase time. erase suspend and resume functions program: 9 p s (typ.) ? minimum number of repetitions for program/erase: ? block erase 100,000 times protection block : 1.0 s (typ.) ? directly drive ttl or cmos condition block : 1.0 s (typ.) ? low power dissipation main block : 1.0 s (typ.) reset mode : 5.0 p a (max.) ? command register input standby mode : 5.0 p a (max.) ? automatic program function operating mode : 35 ma (max.) ? voltage range v cc : 3.0 v + 20 %/-10 % (extend voltage)
preliminary data sheet 2 p p p p PD29F008L ordering information part number access time (max.) protection block package p PD29F008Lgz-b12t-ljh 120 ns the top address 40-pin plastic tsop (i) p PD29F008Lgz-b15t-ljh 150 ns (10 u 20 mm) (normal bent) p PD29F008Lgz-b12b-ljh 120 ns the bottom address p PD29F008Lgz-b15b-ljh 150 ns p PD29F008Lgz-b12t-lkh 120 ns the top address 40-pin plastic tsop (i) p PD29F008Lgz-b15t-lkh 150 ns (10 u 20 mm) (reverse bent) p PD29F008Lgz-b12b-lkh 120 ns the bottom address p PD29F008Lgz-b15b-lkh 150 ns remark for the address locations of the blocks, see the memory maps in erase block layout .
preliminary data sheet 3 p p p p PD29F008L pin configuration (marking side) 40-pin plastic tsop (i) (10 u u u u 20 mm) (normal bent) p p p p PD29F008Lgz-xxxt-ljh p p p p PD29F008Lgz-xxxb-ljh a16 a15 a14 a13 a12 a11 a9 a8 /we /reset ry(/by) a18 a7 a6 a5 a4 a3 a2 a1 a17 gnd nc a19 a10 i/o7 i/o6 i/o5 i/o4 vcc vcc nc i/o3 i/o2 i/o1 i/o0 /oe gnd /ce a0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 nc a0 to a19 : address inputs i/o0 to i/o7 : data inputs/outputs /ce : chip enable /we : write enable /oe : output enable /reset : hardware reset input ry (/by) : ready (/busy) output v cc : supply voltage gnd : ground nc note : no connection note some signals can be applied because this pin is not connected to the inside of the chip.
preliminary data sheet 4 p p p p PD29F008L 40-pin plastic tsop (i) (10 u u u u 20 mm) (reverse bent) p p p p PD29F008Lgz-xxxt-lkh p p p p PD29F008Lgz-xxxb-lkh a17 gnd nc a19 a10 i/o7 i/o6 i/o5 i/o4 vcc vcc nc i/o3 i/o2 i/o1 i/o0 /oe gnd /ce a0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 a16 a15 a14 a13 a12 a11 a9 a8 /we /reset ry(/by) a18 a7 a6 a5 a4 a3 a2 a1 nc a0 to a19 : address inputs i/o0 to i/o7 : data inputs/outputs /ce : chip enable /we : write enable /oe : output enable /reset : hardware reset input ry (/by) : ready (/busy) output v cc : supply voltage gnd : ground nc note : no connection note some signals can be applied because this pin is not connected to the inside of the chip.
preliminary data sheet 5 p p p p PD29F008L input/output pin functions pin name inout/output function a0-a19 input address inputs. a9 input address input. when a9 is at 11.5 v to 12.5 v, the signature mode is accessed. during this mode a0 decodes between the manufacturer and device ids. a0 = l: manufacturer id, a0 = h: device id. i/o0-i/o7 input/output data inputs/outputs. /ce input chip enable signal. high level input: standby mode /oe input output enable sinal. high level input: output disable mode /we input write enable signal. low level input: block erase/program and command input /reset input hardware reset input. low level input: reset mode ry (/by) output the pin for indicating that automatic erase (or automatic program) operation is either in progress or have been completed. this pin is an open-drain output pin. low level output: the device is busy with automatic erase (or automatic program) operation. high level output: the device is ready for new operations, in the erase suspend mode or in reset mode. v cc e supply voltage gnd e ground nc e no connecton: not internally connected. (the signal can be connected.)
preliminary data sheet 6 p p p p PD29F008L erase block layout protection block (16 k bytes) condition block (8 k bytes) condition block (8 k bytes) main block (32 k bytes) main block (64 k bytes) main block (64 k bytes) main block (64 k bytes) main block (64 k bytes) main block (64 k bytes) main block (64 k bytes) main block (64 k bytes) main block (64 k bytes) main block (64 k bytes) main block (64k bytes) main block (64 k bytes) main block (64 k bytes) main block (64 k bytes) main block (64 k bytes) main block (64 k bytes) PD29F008Lxx-xxxt address m fffffh fc000h fbfffh fa000h f9fffh f8000h f7fffh f0000h effffh e0000h dffffh d0000h cffffh c0000h bffffh b0000h affffh a0000h 9ffffh 90000h 8ffffh 80000h 7ffffh 70000h 6ffffh 60000h 5ffffh 50000h 4ffffh 40000h 3ffffh 30000h 2ffffh 20000h 1ffffh 10000h 0ffffh 00000h main block (64 k bytes) main block (64 k bytes) main block (64 k bytes) main block (64 k bytes) main block (64 k bytes) main block (64 k bytes) main block (64 k bytes) main block (64 k bytes) main block (64 k bytes) main block (64 k bytes) main block (64 k bytes) main block (64 k bytes) main block (64 k bytes) main block (64 k bytes) main block (32 k bytes) main block (64 k bytes) condition block (8 k bytes) condition block (8 k bytes) protection block (16 k bytes) PD29F008Lxx-xxxb address m fffffh f0000h effffh e0000h dffffh d0000h cffffh c0000h bffffh b0000h affffh a0000h 9ffffh 90000h 8ffffh 80000h 7ffffh 70000h 6ffffh 60000h 5ffffh 50000h 4ffffh 40000h 3ffffh 30000h 2ffffh 20000h 1ffffh 10000h 0ffffh 08000h 07fffh 06000h 05fffh 04000h 03fffh 00000h
preliminary data sheet 7 p p p p PD29F008L block diagram ry (/by) state control command register v cc detector pgm voltage generator chip enable output enable logic x-decoder stb a d d r e s s l a t c h stb data latch input/output buffers i/o0-i/o7 sector switches erase voltage generator cell matrix y-decoder y-gating timer v cc v ss /reset /we /ce /oe a0-a19
preliminary data sheet 8 p p p p PD29F008L operation mode pin name mode /reset / c e / o e / w e a 9 a 6 a 1 a 0 i/o0-i/o7 product id code, manufacturer code note v ih v il v il v ih v h v il v il v il id product id code, device code note v ih v il v il v ih v h v il v il v ih id read v ih v il v il v ih a9 a6 a1 a0 data output standby v ih v ih uuuuuu hi-z output disable v ih v il v ih v ih uuuu hi-z write v ih v il v ih v il a9 a6 a1 a0 data input enable sector protect v ih v il v h pulse/v ih v h v il v ih v il code verify sector protect v ih v il v il v ih v h v il v ih v il code temporary sector unprotect v h uuuuuuu u reset v il uuuuuuu hi-z note manufacturer and device codes may also be accessed via a command register write sequence. please refer to command definition. remark v h = 12.0 v r 0.5 v u : don?t care (v ih or v il ) see dc characteristics for voltage levels. id = data read from location address during read product id code. 10h : manufacturer code 3eh : device code for a type t 37h : device code for a type b
preliminary data sheet 9 p p p p PD29F008L operation mode (command mode) command sequence first bus write cycle second bus write cycle third bus write cycle fourth bus write cycle fifth bus write cycle sixth bus write cycle address data address data address data address data address data address data reset/read 1 xxxxh f0h eeeeeeeeee read product id code 4 5555h aah 2aaah 55h 5555h 90h ia id eeee program 4 5555h aah 2aaah 55h 5555h a0h pa pd eeee chip erase 6 5555h aah 2aaah 55h 5555h 80h 5555h aah 2aaah 55h 5555h 10h sector erase 6 5555h aah 2aaah 55h 5555h 80h 5555h aah 2aaah 55h ea 30h sector erase suspend 1 xxxxh b0h eeeeeeeeeee sector erase resume 1 xxxxh 30h eeeeeeeeee remark x: v il or v ih ea = block address of memory location to be erased. pa = address of memory location to be programmed. pd = data to be programmed at location pa. ia = identifier address (00000h: address for manufacturer id, 00001h: address for device id). id = data read from location ia during read product id code. 10h : manufacturer code 3eh : device code for a type t 37h : device code for a type b bus cycles
preliminary data sheet 10 p p p p PD29F008L hardware sequence flags status i/o7 i/o6 i/o5 i/o3 i/o2 ry(/by) in progress programming /i/o7 toggle 0010 auto erase 0 toggle 0 1 toggle 0 erase suspend erase sector 1100 toggle 1 non erase sector data data data data data 1 program in suspend /i/o7 toggle 0010 exceeded time limits programming /i/o7 toggle 1010 auto erase 0 toggle 1 1 n/a 0 program in erase suspend /i/o7 toggle 1 0 n/a 0 /data polling (i/o7) /data polling supports system software by indicating the precise end of write or erase cycles. on this support, the next write or erase cycle can be started as soon as previous cycle has completed. ? how to use /data polling (1) after writing data by write operation, fix /we = h. (see /data polling during program or erase operation timing chart.) (2) compare the read data from i/o7 with just before written data. (3) in coincidence with the both data, p PD29F008L will complete its write cycle. then start the next cycle. in case of still in progress, the data on i/o7 is inverted just before written data. (1) after setting erase command by write operation, fix /we = ?h?. (see /data polling during program or erase operation timing chart.) (2) if the read data on i/o7 is ?1?, p PD29F008L has completed its erase cycle, and the other means erase cycle is in progress. toggle bit function (i/o6) toggle bit function supports system software by indicating the precise end of write or erase cycles, too. ? how to use toggle bit function (1) after writing data by command write operation, fix /we = h. (see toggle bit during program /erase algorithm operation timing chart.) (2) watch the read data on i/o6. (3) if the write or erase operation is in progress, the read data from i/o6 will toggle on every reading. and if the operation has completed, the read data will stop toggling. exceed timing limit (i/o5) exceed timing limit function supports system software by indicating the write or erase time has exceeded the specific limits.
preliminary data sheet 11 p p p p PD29F008L ? how to use exceed timing limit function (1) after writing data by command write operation, fix /we = h. (2) watch the read data on i/o5. (3) if the write or erase operation has not successfully completed, i/o5 will indicate 1. sector erase timer (i/o3) sector erase timer function supports system software by indicating the acceptance of sequential sector erase command write. ? how to use sector erase timer function (1) after writing initial sector erase command sequence, watch the data on i/o3. (2) if the data on i/o3 is 1, p PD29F008L will not accept subsequent command until the erase operation is completed as indicated by data polling (i/o7) or toggle bit (i/o6). (3) and if the data on i/o3 is ?0?, p PD29F008L will be able to accept subsequent command.
preliminary data sheet 12 p p p p PD29F008L erase flowchart start write erase cmd sequence data poll from device data = ffh? no yes erasure completed erase algorithm bus operation command sequence comments standby write erase read /data polling to verify erasure standby compare output to ffh.
preliminary data sheet 13 p p p p PD29F008L program flowchart start write program cmd sequence data poll device verify byte? last address? increment address programming completed no no yes yes program algorithm bus operation command sequence comments standby note write program valid address/data read /data polling to verify programming standby note compare data output to data expected note device is either powered-down, erase inhibit, or program inhibit.
preliminary data sheet 14 p p p p PD29F008L electrical characteristics (preliminary) absolute maximum ratings parameter symbol test conditions ratings unit supply voltage v cc with respect to gnd e 0.5 to +5.5 v input voltage v i with respect to gnd e 0.5 note to +5.5 v v i with respect to gnd, a9, /reset, /oe e 0.5 note to +13.5 output voltage v o with respect to gnd e 0.5 note to +5.5 v operating ambient temperature t a e 20 to +70 q c storage temperature t stg e 65 to +125 q c storage temperature (under bias) t bias e 20 to +80 q c note v i , v o = e 2.0 v (min.) for pulse width d 20 ns. caution exposing the device to stress above those listed in absolute maximum ratings could cause permanent damage. the device is not meant to be operated under conditions outside the limits described in the operational sections of this characteristics. exposure to absoulte maximum rating conditions for extended periods may affect device reliability. capacitance (t a = 25 q q q q c, f = 1 mhz) parameter symbol test conditions min. typ. max. unit input capacitance c i v in = 0 v 6.0 7.5 pf output capacitance c o v out = 0 v 8.5 12.0 pf
preliminary data sheet 15 p p p p PD29F008L ac test conditions input waveform (rise/fall time d d d d 10 ns) test points 1.5 v 0 v 3.0 v 1.5 v output waveform test points 1.5 v 0 v 3.0 v 1.5 v output load i/o0 to i/o7 test point 1.3 v 3.3 k w PD29F008L m c l = 100 pf remark c l includes capacitances of the probe and jig, and stray capacitances.
preliminary data sheet 16 p p p p PD29F008L read operation recommended operating conditions parameter symbol min. typ. max. unit supply voltage v cc 2.7 3.0 3.6 v high level input voltage v ih 2.0 v cc +0.5 note1 v low level input voltage v il e 0.5 note2 +0.8 v operating ambient temperature t a e 20 +70 q c notes 1. v ih = v cc +1.0 v (max.) for pulse width d 20 ns 2. v il = e 1.0 v (min.) for pulse width d 20 ns dc characteristics (recommended operating conditions unless otherwise noted) parameter symbol test conditions min. typ. max. unit high level output voltage v oh1 i oh = e 2.0 ma, v cc = v cc (min.) 2.4 v v oh2 i oh = e 2.0 ma, v cc = v cc (min.) 0.85 v cc v i oh = e 100 p a, v cc = v cc (min.) v cc e 0.4 low level output voltage v ol1 i ol = 4.0 ma, v cc = v cc (min.) 0.45 v v ol2 i ol = 5.8 ma, v cc = v cc (min.) 0.45 output leakage current i lo v out = 0 v to v cc , /oe = v ih e 1.0 +1.0 p a input leakage current i li v in = 0 v to v cc e 1.0 +1.0 p a v cc supply current i cca1 v in = v ih /v il fixed 35 ma i cca2 i out = 0 ma, /ce = v il , minimum cycle time 45 ma v cc standby current i ccs1 /ce = /reset = v ih , v cc = v cc (max.) 250 p a i ccs2 /ce t = v cc e 0.2 v 5 p a reset supply current i ccslp /reset = gnd r 0.2 v 5 p a
preliminary data sheet 17 p p p p PD29F008L ac characteristics (recommended operating conditions unless otherwise noted) p PD29F008L-b12 p PD29F008L-b15 min. max. min. max. address to output delay t acc /ce = /oe = v il 120 150 ns /ce to output delay t ce /oe = v il 120 150 ns /oe to output delay t oe /ce = v il 50 55 ns /oe or /ce output float delay t df /ce = v il or /oe = v il 30 40 ns address to output hold t oh /ce = /oe = v il 00ns remark t df is the time from inactivation of /ce or /oe to high-impedance state output. read mode timing chart ax (input) i/ox (output) /ce (input) /oe (input) /we (input) hi-z hi-z data out t oeh t oh t oe note1 t ce note1 t rc valid address t acc note1 t df note2 notes 1. for read operation, the definition of access time is as follows. access time definition /ce input condition /oe input conditon t acc before stabilizing address before (t acc e t oe ) t oe after (t acc e t oe ) t ce after stabilizing address before (t ce e t oe ) t oe after (t ce e t oe ) 2. t df is the time from inactivation of /ce or /oe to high-impedance state output. unit test condition symbol parameter
preliminary data sheet 18 p p p p PD29F008L program and erase operation recommended operating conditions parameter symbol min. typ. max. unit supply voltage v cc 2.7 3.0 3.6 v high level input voltage 1 v ih 2.0 v cc +0.5 note1 v high level input voltage 2 v ih 11.5 12.5 v low level input voltage v il e 0.3 note2 +0.8 v operating ambient temperature t a e 20 +70 q c notes 1. v ih = v cc +0.6 v (max.) for pulse width d 20 ns 2. v il = e 0.6 v (min.) for pulse width d 20 ns dc characteristics (recommended operating conditions unless otherwise noted) parameter symbol test conditions min. typ. max. unit high level output voltage v oh1 i oh = e 2.0 ma 2.4 v v oh2 i oh = e 2.0 ma 0.85 v cc v i oh = e 100 p av cc e 0.4 low level output voltage v ol1 i ol = 4.0 ma, v cc = v cc (min.) 0.45 v v ol2 i ol = 5.8 ma, v cc = v cc (min.) 0.45 output leakage current i lo v out = 0 v to v cc , /oe = v ih e 1.0 +1.0 p a input leakage current i li v in = 0 v to v cc e 1.0 +1.0 p a v cc supply current standby i ccs1 /ce = /reset = v ih 250 p a i ccs2 /ce = /reset = v cc r 0.2 v 5 p a reset i ccslp /reset = gnd r 0.2 v 5 p a read i cca1 i out = 0 ma, /ce = v il , v in = v ih /v il fixed 35 ma i cca2 i out = 0 ma, /ce = v il , minimum cycle time 45 ma program i ccp 35 ma erase i cce 35 ma low v cc lock-out voltage v lko 2.3 2.5 v
preliminary data sheet 19 p p p p PD29F008L ac characteristics (1) (/we control) (recommended operating conditions unless otherwise noted) p PD29F008L-b12 p PD29F008L-b15 min. typ. max. min. typ. max. cycle time t cw1 120 150 ns address setup time 1 t as1 00ns address hold time 1 t ah1 50 65 ns data input setup time 1 t ds1 50 65 ns data input hold time 1 t dh1 00ns /oe setup time t oes 00ns /oe hold time read t oeh 00ns toggle and /data polling 10 10 ns read recovery time before write t oehc 00ns /ce setup time t ces 00ns /ce hold time (v il )t cel 00ns write pulse width t wep 50 65 ns /we hold time t weh 30 35 ns total program time t apt 99 p s total erase time t aetb 11s v cc setup time t vcs 50 50 p s write recovery time from ry (/by) t rb 00ns /reset low time t rl 500 500 ns /reset high time before read t prhh 50 50 ns /reset to sleep time t slp 20 20 p s program/erase valid to ry (/by) delay t busy 90 90 ns remark duration of the program or erase operation is variable and is calculated in the internal algorthms. parameter symbol unit
preliminary data sheet 20 p p p p PD29F008L write operation timing chart ax /ce /oe /we i/ox v cc t ds1 t dh1 t oesw t ces t weh t apt or t aetb t cw1 t as1 t ah1 t wep d in i/07 d out t df t oh t oe t ce t rc remarks 1. d in is data input to the device. 2. i/o7 is the output of the complement of the data written to the device. 3. d out is the output of the data written to the device.
preliminary data sheet 21 p p p p PD29F008L chip/sector erase operation timing chart ax /ce /oe /we i/ox v cc t ds1 t dh1 t oehc t ces t weh 5555h t cw1 t as1 t ah1 t wep 55h aah 80h aah 55h 10h for chip erase 30h 2ah 5555h 5555h 2ah ea remarks 1. ea is the sector address for sector erase. addresses = dont care for chip erase. 2. these waveforms are for the word mode. /data polling during program or erase operation timing chart i/ox /ce /oe /we data t oeh t oe t apt or t aetb t ce hi-z t oh t df t wel data remark i/o7 = valid data (the device has completed the program or erase operation).
preliminary data sheet 22 p p p p PD29F008L toggle bit during program/erase algorithm operation timing chart i/o6 /ce /we /oe t oeh t dh t de remark i/o6 stops toggling (the device has completed the program or erase operation). ry (/by) timing chart program/erase operation /ce /we ry(/by) t busy the rising edge of the last /we signal programming or erase operations /reset timing chart /reset t rp t ready
preliminary data sheet 23 p p p p PD29F008L temporary sector unprotect flowchart start perform erase or program operations temporary sector unprotect completed note2 /reset = v ih note1 /reset = v ih notes 1. all protected sectors unprotected. 2. all previously protected sectors are protected once again. temporary sector unprotect timing chart /reset 12 v 5 v /ce /we r (/b) program or erase command sequence t vlht
preliminary data sheet 24 p p p p PD29F008L ac characteristics (2) (/ce control) (recommended operating conditions unless otherwise noted) p PD29F008L-b12 p PD29F008L-b15 min. typ. max. min. typ. max. write cycle time t cw2 120 150 ns address setup time 2 t as2 00ns address hold time 2 t ah2 50 50 ns data input setup time 2 t ds2 50 50 ns data input hold time 2 t dh2 00ns /oe setup time t oes 00ns /oe hold time read t oeh 00ns toggle and /data polling 10 10 ns read recovery time before write t oehc 00ns /we setup time t wes 00ns /we hold time (v il )t wel 00ns /ce pulse width t cep 50 50 ns /ce pulse width high t ceh 20 20 ns total program time t apt 99 p s total erase time note t aetb 110 110s note this does not include the preprogramming time. parameter symbol unit
preliminary data sheet 25 p p p p PD29F008L alternate /ce controlled write operation timing chart ax /we /oe /ce data 3.0 v t oehc t cep t dh t ds t apt t ceh t wes 5555h t cw2 t as t ah pa a0h /data polling pa pd i/o7 d out remarks 1. pa is address of the memory location to be programmed. 2. pd is data to be programmed at byte address. 3. i/o7 is the output of the complement of the data written to the device. 4. d out is the output of the data written to the device. 5. figure indicates last two bus cycles of four bus cycle sequence. 6. these waveforms are for the word mode.
preliminary data sheet 26 p p p p PD29F008L package drawings 40 pin plastic tsop( i ) (10x20) item millimeters inches b c 0.5 (t.p.) 0.020 (t.p.) 0.45 max. 0.018 max. d 0.22?.05 0.009 +0.002 ?.003 g 0.97?.05 0.038 +0.003 ?.002 j 0.8?.1 0.031 +0.005 ?.004 k 0.145?.05 0.006 +0.004 ?.002 l 0.5 0.020 m 0.10 0.004 a 10.0?.1 0.394 +0.004 ?.005 i 18.4?.1 0.724 +0.005 ?.004 p 20.0?.2 0.787 +0.009 ?.008 r3 +5 ? n 0.10 0.004 s40gz-50-ljh1 s 1.2 max. 0.047 max. u 0.6?.15 0.024 +0.006 ?.007 t 0.25 0.010 m b q r k j g d detail of lead end n t s u l c m 3 +5 ? notes 1. controlling dimention millimeter. 2. each lead centerline is located within 0.08 mm (0.003 inch) of its true position (t.p.) at maximum material condition. 3. "a" excludes mold flash. (includes mold flash : 10.4 mm max. <0.410 inch max.>) 1 20 40 21 s a p i s q 0.1?.05 0.004 +0.002 ?.003
preliminary data sheet 27 p p p p PD29F008L 40 pin plastic tsop( i ) (10x20) item millimeters inches b c 0.5 (t.p.) 0.020 (t.p.) 0.45 max. 0.018 max. d 0.22?.05 0.009 +0.002 ?.003 g 0.97?.05 0.038 +0.003 ?.002 j 0.8?.1 0.031 +0.005 ?.004 k 0.145?.05 0.006 +0.002 ?.003 l 0.5 0.020 m 0.10 0.004 notes 1. controlling dimention millimeter. a 10.0?.1 0.394 +0.004 ?.005 i 18.4?.1 0.724 +0.005 ?.004 p 20.0?.2 0.787 +0.009 ?.008 r3 +5 ? n 0.10 0.004 s40gz-50-lkh1 s 1.2 max. 0.047 max. u 0.6?.15 0.024 +0.006 ?.007 t 0.25 0.010 m b q r k j g d detail of lead end n t s u l c m 3 +5 ? 2. each lead centerline is located within 0.08 mm (0.003 inch) of its true position (t.p.) at maximum material condition. 3. "a" excludes mold flash. (includes mold flash : 10.4 mm max. <0.410 inch max.>) 40 21 1 20 s a s p i q 0.1?.05 0.004 +0.002 ?.003
preliminary data sheet 28 p p p p PD29F008L [memo]
preliminary data sheet 29 p p p p PD29F008L [memo]
preliminary data sheet 30 p p p p PD29F008L [memo]
31 p p p p PD29F008L notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed imme- diately after power-on for devices having reset function.
p p p p PD29F008L no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec corporation. nec corporation assumes no responsibility for any errors which may appear in this document. nec corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. no license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec corporation or others. while nec corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. to minimize risks of damage or injury to persons or property arising from a defect in an nec semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. nec devices are classified into the following three quality grades: "standard", "special", and "specific". the specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. the recommended applications of a device depend on its quality grade, as indicated below. customers must check the quality grade of each device before using it in a particular application. standard: computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots special: transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) specific: aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. the quality grade of nec devices is "standard" unless otherwise specified in nec's data sheets or data books. if customers intend to use nec devices for applications other than those specified for standard quality grade, they should contact an nec sales representative in advance. anti-radioactive design is not implemented in this product. m4 96. 5

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